Joint Rewriting and Error Correction in Flash Memories

The current NAND flash architecture requires block erasure to be triggered in order to decrease the level of a single cell inside a block. Block erasures degrade the quality of cells as well as the performance of flash memories. One solution is to model flash memories as write-once memories (WOM) where the level of a cell can only be increased. Various coding schemes for WOM can then be applied so that a block of cells can be rewritten multiple times without triggering a block erasure. Yet, due to the high storage density of flash memories, programming and reading memory cells bring nontrivial disturbance and interference, which introduce errors to the data. Therefore, both rewriting and error correction are important technologies for keeping flash memories efficient and reliable. However, coding schemes that combine them have been limited. This paper presents a new coding scheme that combines rewriting and error correction for the write-once memory model. Its construction is based on polar codes, and it supports any number of rewrites and corrects a substantial number of errors. The code is analyzed for the binary symmetric channel, and experimental results verify its performance. The results can be extended to multi-level cells and more general noise models.